1. Field of the Invention
The present invention generally relates to an active balun circuit, in particular, to an active balun circuit with a high frequency and a high linearity used in a complementary metal oxide semiconductor (CMOS) technology.
2. Description of Related Art
An active balun circuit is used to generate two output signals, which have the same intensity, but have a phase difference of 180 degrees. In addition, the active balun circuit is mainly applied in a radio frequency (RF) receiver.
Theoretically, a conventional active balun circuit can generate two output signals that have the same intensity but have a phase difference of 180 degrees. However, in practice, when operating at a high frequency, the conventional active balun circuit may not be able to generate two signals that have the same intensity but have a phase difference of 180 degrees for the RF receiver. Therefore, such undesirable feature may cause a serious impact on the waveforms generated by a mixer in the RF receiver, for example, the mirror image is not completely eliminated, or the isolation is poor.
FIG. 1 is a circuit diagram of a conventional active balun circuit 10. Referring to FIG. 1, the conventional active balun circuit 10 includes transistors M1 and M2, a current source CS1, capacitors C1 and C2, resistors R1 and R2, an input end INPUT1, and output ends OUTPUTP1 and OUTPUTN1. The capacitor C1 is coupled between the input end INPUT1 and a gate of the transistor M1, and the capacitor C2 is coupled between a gate of the transistor M2 and a ground end GND. The resistor R1 is coupled between a voltage supply end VDD and the output end OUTPUTN1, and the resistor R2 is coupled between the voltage supply end VDD and the output end OUTPUTP1. The output ends OUTPUTN1 and OUTPUTP1 are coupled to drains of the transistors M1 and M2 respectively. The current source CS1 is coupled between sources of the transistors M1 and M2 and the ground end GND.
The input end INPUT1 receives an input signal. The dotted line S1 shows a path in which an output signal is generated at the output end OUTPUTN1 by the input signal after passing through the transistor M1, and the dotted line S2 shows a path in which an output signal is generated at the output end OUTPUTP1 by the input signal after passing through the transistor M2. Generally, in order to improve the linearity of the conventional active balun circuit 10, the transistors M1 and M2 are often designed into small transistors, and the biases on the transistors M1 and M2 are often designed at a low level.
Though the above design improves the linearity of the conventional active balun circuit 10, when operating at a high frequency, the conventional active balun circuit 10 may generate a phase difference deviated from 180 degrees between the output ends OUTPUTN1 and OUTPUTP1. To put it simply, the conventional active balun circuit 10 cannot achieve optimal linearity, bandwidth, and phase difference features at the same time.
To solve the above problem, U.S. Pat. No. 6,566,961 provides an active balun circuit, which uses two stages of amplifier circuits to solve the above problem. The amplifier circuit in the first stage is a phase compensation circuit, and the amplifier circuit in the second stage is a gain compensation circuit. The gain compensation circuit uses two feedback capacitors to compensate the gain error. Though the active balun circuit of the U.S. Pat. No. 6,566,961 can effectively solve the above problem, as two stages of amplifier circuits are needed, the active balun circuit has a relatively large chip size and large power consumption.
FIG. 2 is circuit diagram of an active balun circuit 20 proposed by Chuang Zhang. The active balun circuit 20 was disclosed in the Master's Thesis entitled “CMOS Front-End Amplifier for Broadband DTV Tuner” published in May 2005 at Texas A&M University by Chuang Zhang.
The active balun circuit 20 includes transistors M3 and M4, a current source CS2, capacitors C3, C4, and C5, resistors R3 and R4, an input end INPUT2, and output ends OUTPUTP2 and OUTPUTN2. The input end INPUT2 receives an input signal. The capacitor C3 is coupled between the input end INPUT2 and a gate of the transistor M3, the capacitor C4 is coupled between a gate of the transistor M4 and a ground end GND, and the capacitor C5 is coupled between the output end OUTPUTP2 and the gate of the transistor M3. The resistor R3 is coupled between a voltage supply end VDD and the output end OUTPUTN2, and the resistor R4 is coupled between the voltage supply end VDD and the output end OUTPUTP2. The output ends OUTPUTN2 and OUTPUTP2 are coupled to drains of the transistors M3 and M4 respectively. The current source CS2 is coupled between sources of the transistors M3 and M4 and the ground end GND.
The active balun circuit 20 uses the feedback capacitor C5 to compensate the phase error generated at a high frequency, and makes use of the characteristics of a common gate configuration to reduce the gain error. However, though the active balun circuit 20 reduces the phase error generated at a high frequency and improves the linearity, the common gate configuration may narrow the overall operation bandwidth of the active balun circuit 20.
As described above, the active balun circuits still need to be improved. Currently, many manufacturers and researchers are still working on the development of an active balun circuit that has a high linearity and a small size, and can operate at a high frequency.